1. Field of the Invention
The present invention relates generally to microprocessors, and more specifically to a method and apparatus for the transfer of data across disparate within a micro-chip.
2. Description of the Related Art
In a multi-processor environment, it is important to transmit data between processors. For example, system on a chip (SoC) technology enables the packaging of all the parts and electronic circuits for a system on an integrated circuit. This technology may be used for cell phones, digital cameras, and other consumer electronics. Here, multiple processors may be in communication with each other. The highly integrated micro-chips operate various parts of the chip at different frequencies. The conventional approach to the communication across different frequency domains is to treat each clock as completely independent and the interface as completely asynchronous.
FIG. 1 is a simplified schematic of an apparatus for accommodating the multiple clock domains associated with a system on a chip. Region 100 is associated with clock domain A while region 102 is associated with clock domain B. Input data X 106 comes into storage cell F1 108 operating at a frequency associated with clock domain A. Double synchronizer 104 includes storage cells F2 110 and F3 112 which are driven at a frequency associated with clock domain B. The configuration of double synchronizer 104 enables protection from a metastable condition occurring between storage cell F2 110 and F3 112 through a logic threshold adjustment.
Therefore, between each clock domain three types of storage cells are necessary and the special design, i.e., design complexity, of the double synchronizer configuration and storage cells F2 110 and F3 112. Furthermore, the amount of time associated with converting input data X to output data Y is non-deterministic. That is, due to clock skew between clock domain A and clock domain B the timing can not be determined. Thus, for scan testing or debugging purposes deterministic behavior is achieved by forcing clock A and clock B to be the same through special test circuitry. However, this does not produce the actual functionality of operating conditions as the timing of events are being changed. Therefore, the chip may pass during the system debug but fail during functional testing. Another shortcoming of this technique is the relatively high overhead and transfer latency associated with the technique.
In light of the foregoing, it is desired to implement a design and scheme to communicate across frequency domains with a minimum of overhead with respect to the design and the latency of the data transfer across the frequency domains.